Asus MAXIMUS V GENE - Manuel (Page 88)

ASUS MAXIMUS V GENE 3-9
Chapitre 3
DRAM WRITE to READ Delay [Auto]
Configuration options: [Auto] [1 DRAM Clock] – [15 DRAM Clock]
DRAM CKE Minimum pulse width [Auto]
Configuration options: [Auto] [1 DRAM Clock] – [15 DRAM Clock]
DRAM CAS# Write Latency [Auto]
Configuration options: [Auto] [1 DRAM Clock] – [15 DRAM Clock]
DRAM RTL (CHA) [Auto]
Configuration options: [Auto] [1 DRAM Clock] – [63 DRAM Clock]
DRAM RTL (CHB) [Auto]
Configuration options: [Auto] [1 DRAM Clock] – [63 DRAM Clock]
DRAM IO-L (CHA) [Auto]
Configuration options: [Auto] [Delay 1 Clock] – [Delay 15 Clock]
DRAM IO-L (CHB) [Auto]
Configuration options: [Auto] [Delay 1 Clock] – [Delay 15 Clock]
Third Timings
tWRDR (DD) [Auto]
Configuration options: [Auto] [1 DRAM Clock] – [8 DRAM Clock]
tRWDR (DD) [Auto]
Configuration options: [Auto] [1 DRAM Clock] – [8 DRAM Clock]
tRWSR [Auto]
Configuration options: [Auto] [1 DRAM Clock] – [8 DRAM Clock]
tRR (DD) [Auto]
Configuration options: [Auto] [1 DRAM Clock] – [8 DRAM Clock]
tRR (DR) [Auto]
Configuration options: [Auto] [1 DRAM Clock] – [8 DRAM Clock]
tRRSR [Auto]
Configuration options: [Auto] [4 DRAM Clock] – [7 DRAM Clock]
tWW (DD) [Auto]
Configuration options: [Auto] [1 DRAM Clock] – [8 DRAM Clock]
tWW (DR) [Auto]
Configuration options: [Auto] [1 DRAM Clock] – [8 DRAM Clock]
tWWSR [Auto]
Configuration options: [Auto] [4 DRAM Clock] – [7 DRAM Clock]
MISC
MRC Fast Boot [Enabled]
Configuration options: [Enabled] [Disabled]
DRAM CLK Period [Auto]
Configuration options: [Auto] [1] – [14]
Transmitter Slew (CHA) [Auto]
Configuration options: [Auto] [1] – [7]