Chapitre 3, 2 chipset, Channel interleaving [xor of address bit – Asus M4N98TD EVO Manuel d'utilisation

Page 75: Memclk tristate c3/atlvid [disabled, Dct unganged mode [always, Power down enable [disabled, Northbridge chipset configuration, Dram controller configuration

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ASUS M4N98TD EVO

3-19

Chapitre 3

3.6.2

Chipset

Ce menu vous permet de modifier les paramètres du chipset. Sélectionnez un élément puis

appuyez sur <Entrée> pour en afficher le sous-menu.

Channel Interleaving [XOR of Address bit]

Options de configuration : [Disabled] [Address bits 6] [Address bits 12]

[XOR of Address bits [20:16, 6]] [XOR of Address bits [20:16, 9]]

MemClk Tristate C3/ATLVID [Disabled]

Options de configuration : [Disabled] [Enabled]

Memory Hole Remapping [Enabled]

Options de configuration : [Disabled] [Enabled]

DCT Unganged Mode [Always]

Options de configuration : [Auto] [Always]

Power Down Enable [Disabled]

Options de configuration : [Disabled] [Enabled]

Power Down Mode [Channel]

Cet élément n’apparaît que si l’option précédente a été activée. Options de

configuration : [Channel] [Chip Select]

NorthBridge Chipset Configuration

BIOS SETUP UTILITY

Advanced

NorthBridge Chipset Configuration

DRAM Controller Configuration

ECC Configuration

DRAM Controller Configuration

BIOS SETUP UTILITY

Advanced

DRAM Controller Configuration

Channel Interleaving

[XOR of Address bit]

MemClk Tristate C3/ATLVID

[Disabled]

Memory Hole Remapping

[Enabled]

DCT Unganged Mode

[Always]

Power Down Enable

[Disabled]

Enable Channel Memory

Interleaving

Options for NB

Advanced Chipset Settingsz

NorthBridge Configuration

SouthBridge Configuration

BIOS SETUP UTILITY

Advanced

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